A PLL (Phase Locked Loop) circuit is used for example as a frequency synthesizer for generating a sampling clock for an AD (analog-to-digital) converter, and is mounted on almost every semiconductor device called SOC (System on Chip). A PLL circuit for generating a clock having a small amount of phase jitter is used in order for the AD converter to perform AD conversion with high accuracy.
Generally, the PLL circuit includes a voltage controlled oscillator (hereinafter referred to as “VCO”), a charge pump (CP), and a phase frequency detector (PFD). This type of PLL circuit involves three main factors which affect jitter which are phase noise of the VCO, power supply noise and reference spurious (sometimes called reference leak).
Among these factors, the phase noise of the VCO may be reduced by increasing power consumption by the VCO, for example. Also, the power supply noise may be reduced by power supply disconnection, a bypass capacitor, or the like.
However, a further reduction in the jitter involves the problem of the reference spurious.
A main cause of occurrence of the reference spurious is that a charge pump current flows in order to compensate for variations in a control voltage of the VCO caused by leak or the like, and thereby temporary variations in the control voltage occur. When the PLL circuit is locked (or phase-locked), the control voltage repeats the following variations at every comparison cycle; specifically, the control voltage varies greatly at the instant of phase comparison and then varies gradually.
Heretofore, a low-pass filter (LPF) of the PLL circuit has been devised in order to reduce the jitter caused by the reference spurious. For example, there have been proposals of a method which involves sampling a voltage of a low-pass filter by a switched capacitor filter, and supplying the sampled voltage to a VCO, and a method which involves performing pipeline processing for charging or discharging operations for plural capacitances connected in parallel.    [Patent Document 1] Japanese Laid-open Patent Publication No. 11-308105    [Patent Document 2] Japanese Laid-open Patent Publication No. 2008-35451